MMCM Feedback Path and Compensation Mode - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

The following table identifies the Vivado tools behavior for the feedback path based on the compensation mode for the MMCM. The COMPENSATION attribute values are documented for informational purposes only, and the Vivado tools automatically select the appropriate compensation based on the circuit topology.

Table 1. MMCM Compensation Modes
COMPENSATION Vivado Tool Behavior

The same clock root is assigned to the net driven by the feedback path global clock buffer and by all global clock buffers directly connected to the CLKOUT0 pin. The Vivado tools do not automatically match the insertion delay with the other MMCM/XPLL outputs.

To perform delay matching and clock root matching with other MMCM/XPLL output pins, it is necessary to use the CLOCK_DELAY_GROUP and USER_CLOCK_ROOT constraints.


A feedback path is not needed for INTERNAL compensation. Having a feedback path with a global clock buffer is an unnecessary use of clocking resources. This could negatively impact QoR in designs with high clocking utilization.

The Vivado tools attempt to remove unnecessary feedback path global clock buffers. In some cases, the Vivado tools are unable to remove the unnecessary feedback path global clock buffer, and you must remove the feedback path global clock buffers manually.

EXTERNAL The MMCM can be configured for external deskew where the feedback board trace matches the trace to the external components. The external delay value is set using the following XDC constraint:
set_external_delay -from <output_port> -to <input_port> <external_delay_value>
The external delay value is used by the Vivado tools in the calculation of the MMCM compensation delay.
Note: The XPLLs and DPLLs do not have a COMPENSATION property. DPLLs can provide a negative hold for all I/O registers of an entire HDIO bank via the ZHOLD property when using the phase detector deskew circuitry. The ZHOLD feature of the DPLL is not supported for XPIO banks.