IDDRE1 Clocking - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

For IDDRE1 clocking in Versal devices, maximum skew requirements exist between the clock and inverted clock pins. To meet the maximum skew requirements, AMD recommends using a single net for the clock and inverted clock pins when using the local inversion.

The following figure shows the optimal configuration that uses the local inversion on the CB pins of the IDDRE1. Using the optimal configuration guarantees that the maximum skew requirement is met while using fewer global clock resources.

Figure 1. Optimal Clocking Topology for IDDRE1