GT Interface Clocking - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Each GT interface requires several clocks, including some clocks that are shared across bonded GT*_QUAD cells located in one or several GT quads. The GT quads are located in the left and rightmost clock regions in the Versal device. Each of the clock regions includes two GT quads, 24 BUFG_GT/MBUFG_GT clock buffers, and one DPLL. Most GT clocks have a low fanout with loads placed locally in the clock region next to the associated GT*_QUAD. Some GT clocks drive loads across the entire device and require the utilization of clock routing resource in many clock regions.