Floorplanning Constraints for Dynamic Function eXchange - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Optimal floorplanning is critical to ensuring timing closure and avoiding routability issues in DFX designs. Rules related to I/O banks in DFX floorplanning can also influence board pinout planning. Following are key areas to consider in floorplanning a DFX design:

  • Pblocks

    When floorplanning for DFX partitions, allocate the maximum amount of resources to the RP Pblock, keeping minimal resources in the static region to meet the platform compilation requirement.

    The same clock region can be shared between multiple RPs by splitting the clock region horizontally (upper half and lower half), except for the half clock regions present at the top of the PL in some Versal devices.

    Programmable unit (PU) granularity is typically the tile itself, except for I/Os where granularity is a full I/O bank. This fine granularity allows greater flexibility in floorplanning. For more information on the PU, see this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

    To avoid bleed over of static nets to the RP, you can create a Pblock for that static region with contain routing enabled. However, this approach requires additional considerations with regard to routability of the static logic. For details, see Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

  • I/Os

    In Versal devices, declaring one static I/O in an I/O bank forces all I/O sites of that I/O bank to the static region, but clocking resources can still be reconfigured. In previous devices, I/O and clocking resources were bundled in the same PU so that all I/O and clocking resources were either all static or all reconfigured and were not allowed to be in separate domains.

  • Clocking

    If RP uses remote clocking tile and needs to cross over another RP, the clock track usage is limited based on its split between the RPs. Use the DPLL in the GT clock region which could be local to RP instead of MMCM of the horizontal clock region at the bottom of the device.

    For more information on clock region, see this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

  • Partition pins

    In a DFX design, signals between the reconfigurable module (RM) and static region are called boundary signals. All RM pins must have a partition pin location (PPLOC) deposited on the boundary signal by the placer. The only exceptions are dedicated paths between hard primitives. The partition pin is the physical interface on the PL that separates the static and reconfigurable portions of a boundary signal. For more information on PPLOCs, see this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

    The presence of partition pins reduces the solution space for the router, because the corresponding boundary net is always forced to route through the partition pin. To alleviate this issue, the DFX flow includes expanded routing. Expanded routing is the additional routing footprint for an RP that can include routing tiles from the static region. For more information on expanded routing, see this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

    You can also reduce the local density of partition pins to avoid routing challenges when implementing future reconfigurable module variants. There are multiple properties like HD.PARTPIN_RANGE and HD.PARTPIN_LOCS to control the placement of partition pins.

For more information on Pblock guidelines, I/O planning, clocking, and PPLOC reduction, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).