Designing with HBM Devices - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

The AMD Versalâ„¢ HBM devices are designed to enable convergence of fast memory, adaptable compute, and secure connectivity in a single platform. With the integration of HBM2e DRAM, the Versal HBM series provides 8x more bandwidth at 63% lower power than DDR5. It delivers up to 820 GBps memory bandwidth and 32 GB capacity to minimize power, area, and latency for compute-intensive applications. Integrated HBM is globally accessible from anywhere on the device by a programmable NoC. With an integrated memory controller and enhanced hardened switch function, any memory location is accessible from any port.

The Versal HBM controller provides access to one or two stacks depending on the HBM device type, up to 128 Gb (16 GB) for eight high stacked devices. Eight independent HBM controllers are connected to a single stack. The HBM controller interfaces to user logic in PL via the NoC. The NoC allows global addressing to the entire HBM stack from any master connected to the NoC. The NoC IP core can be configured to include a subset or all the integrated HBM controllers.

In some applications, the NoC might not be sufficient for HBM connectivity, so some data has to go through the NoC and some through fabric.