Design Planning Considerations for the Platform-Based Design Flow - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

When using the Versal adaptive SoC platform-based design flow, you must partition your design between the hardware platform, created in the Vivado tools, and a subsystem, created and incorporated into the platform by the AMD Vitis™ environment. To be successful using this design flow, you must correctly identify the sections of the design to be contained in the platform and the other sections to be incorporated via the Vitis environment. In general, common shared resources are expected to be in the platform, and the specialized components of the design are likely to be incorporated using the Vitis environment.

Common examples of IP contained in the platform include:

  • CIPS
  • NoC interconnect
  • Clocking
  • Reset
  • Interrupt controllers

The Vitis environment can accept several types of design sources including:

  • Packaged BD
  • Packaged RTL
  • HLS C code
  • AI Engine kernel code
Note: The connectivity between AI Engine kernels as well as between AI Engine kernels and the platform are defined in a graph file.

The following figure shows an example of the platform-based design flow.

Figure 1. Platform-Based Design Flow