Design Planning Considerations for Tandem Configuration - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Tandem configuration is a staged configuration that brings up the PCIe protocol less than 100 ms after power to Versal adaptive SoC is stable. This is achieved using a stage 1 programmable device image (PDI). The rest of the device, including the PL, can be downloaded by the user application as a stage 2 PDI. In Versal adaptive SoC, Tandem configuration is accomplished using the CPM integrated block. Tandem configuration supports the Tandem PCIe and Tandem PROM modes. For more information, see the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).

Unlike previous architectures, stage 1 configuration elements are hardened blocks in the CPM. The CPM portion of the CIPS IP contains an option to enable Tandem configuration. You can select either Tandem PROM or Tandem PCIe. The programmable device image (PDI) is constructed with two partitions: stage1 and stage2. The stage1 portion of the design includes configuration of the PMC and CPM, and the stage2 portion of the design includes everything else. If you select the Tandem PROM mode, the stage1 and stage2 portions are generated in a single PDI file and can be loaded automatically through a configuration flash interface. If you select the Tandem PCIe mode, the stage1 PDI file is loaded through the configuration flash, and the stage2 PDI is loaded through the PCIe link. Both Tandem PCIe and DFX over PCIe solutions require additional design connectivity and host interaction to configure the device.