Design Creation with Block Designs - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

The AMD Vivado™ IP integrator enables you to create complex system designs by instantiating and connecting IP blocks from various sources. You can create designs either interactively on a canvas GUI or programmatically through a Tcl programming interface. Following are the primary advantages of creating designs in the IP integrator:

  • Designs are constructed at the interface level (for enhanced productivity) but can also be manipulated at the port level (for precision design manipulation).
  • Designs are created in a correct-by-construction manner, which means automatic design rule checks (DRCs) in the tool can detect issues earlier in the design cycle.
  • Automation features that configure and connect blocks save development time.
  • Collaboration features, such as block design containers, enable team design and reusability.

In addition, IP integrator provides the following advantages for AMD Versal™ adaptive SoC designs:

  • Automatic configuration and connectivity for CIPS and NoC Versal device-specific blocks.
    Note: You are not required to create your entire design in IP integrator. However, at a minimum, you must create this portion of your design in a block design. The resulting block design can then be instantiated and used with other RTL sources. IP integrator is required for advanced capabilities, such as Dynamic Function eXchange (DFX).
  • Versal device transceivers configuration, sharing, and integration in GT-based IP.
  • Easier complete design integration for various Versal device domains (PL, PS, AI Engine).
  • Seamless interaction with AMD Vitis™ tools allowing export of custom hardware platforms.

The following sections provide best practices and information to help you achieve better results in IP integrator as part of your Versal adaptive SoC design.

Note: As part of design creation, design constraints must be reviewed and completed in the Vivado Design Suite after running synthesis.
Important: This section describes how to best create a hardware design using the AMD Vivado™ IP integrator. This is the primary design type for non-AI Engine-based projects. A platform design is similar but allows the AMD Vitis™ linker to add additional PL and AI Engine blocks to the design. Platform designs are required for AI Engine-based projects but are optional for non-AI Engine-based projects. Creating a platform design has additional requirements, as described in the Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400).