Dealing with High Levels of Logic - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Identifying long logic paths is useful to diagnose difficult QoR challenges. Estimated net delays post-synthesis are close to the best possible placement. To evaluate if a path with high logic-level delay is meeting timing, you can generate timing reports with no net delay. Timing closure cannot be achieved on paths that are still violating timing with no net delays.

Note: For more information, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).