Creating a Hardware Platform for the Platform-Based Design Flow - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

An extensible platform is the foundation of the platform-based design flow in the Vitis environment. The platform insulates application developers from the details of the low-level infrastructure and lets them focus on development of a specific function in the processing system, such as software, AI Engine graph, or PL kernel logic. Using the Vitis environment, a developer can add AI Engine and PL kernels to an extensible platform. The kernels added using the Vitis environment automatically have access to memories, interrupt controllers, resets, and clocking resources contained in the platform.

A Vitis extensible platform comprises both a hardware component and a software component. The hardware components of a platform are designed using the Vivado IP integrator. The software components of a platform are created using the Vitis or PetaLinux tool chain.

This section describes the flow used to create and configure hardware components of a platform using the IP integrator. For information on creating the software platform and packaging the entire platform, see this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

The design created using the IP integrator must capture the foundational Versal adaptive SoC hardware IP blocks, including CIPS, NoC, I/O controllers, and AI Engine array. The design must also expose logical interfaces to which kernels can be connected to later on, using the Vitis v++ linker. The processors, memory, and all external board interfaces are configured using a combination of AMD IP, custom IP, and RTL.

The following figure shows an example of the block diagram for a hardware platform.

Figure 1. Hardware Platform Block Diagram Example

Following are the steps to build a hardware platform in IP integrator.

Figure 2. Creating a Hardware Platform
  1. Instantiate the necessary IP to create the hardware portion of the platform.

    This might include properly configuring the CIPS, NoC, Processor System Reset Module, and Clocking Wizard IP to meet the needs of the intended platform. The input and output pins of these blocks are used by the hardware functions. Hardware functions are built by the Vitis tools at a later step.

  2. After building a block design in the IP integrator, declare and add platform (PFM) interfaces and properties on the IP blocks before exporting the design as a hardware platform to the Vitis environment.

    These platform settings include clocking, interrupts, resets, memory, and processor AXI interfaces required for hardware functions within the Vitis environment. The IP integrator GUI provides a Platform Setup window to declare these interfaces along with their properties.

    Following are requirements for the PFM step:

    • There must be at least one enabled AXI port master interface within the platform.
    • A platform can have one or more clocks. There must be at least one enabled clock interface within the platform. If a hardware function uses a particular clock, then it uses the synchronized reset output for that clock.
    • Interrupts are typically connected in the platform via the Concat block.
  3. Export the hardware definition (XSA) to the Vitis environment after generating the design.

    This exports the necessary XML files needed for the Vitis tools to interpret the IP used in the design and also exports the memory mapping from the processor perspective.

After creating the hardware platform, you must package the exported XSA with the software components to create the entire Vitis platform for use with the v++ compiler/linker.

For more information on IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).