Coding Recommendations for Creating and Packaging RTL Kernels for the Platform-Based Design Flow - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

The platform-based design flow for Versal adaptive SoC makes it easy to use existing RTL code or Vivado IP as Vitis kernels. Vitis kernels are well-formalized design blocks, which can be automatically integrated in a correct-by-construction manner to extensible platforms using the Vitis v++ linker.