Checking for Reset Signals on the Address/Read Data Registers - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Memory arrays should not be reset. Only the output of the RAM can tolerate a reset. The Versal architecture can handle either asynchronous or synchronous resets on the output of the RAM. However, the output register and the optional output register must have the same asynchronous reset.

The following figure highlights an example of what to avoid to ensure correct inference of RAMs and output registers. The register on the read address will be used to create the block RAM, but the extra register on the output will not be used in the Block RAM because its asynchronous reset does not match the RAM output reset.

Figure 1. Checking for Reset On Address/Read Data Registers