Center Clock Root in Horizontal Direction - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2023-11-15
Version
2023.2 English

The maximum clock extent that affects Fmax is the sum of the fabric clock regions traversed by the clock routing and distribution network. The horizontal route through the XPIO clock regions does not contribute to a decrease in Fmax. Hence, the Fmax can be improved by assigning the clock root in the center most vertical NoC column for a given clock network. In the example below, a BUFGCE in clock region X12Y0 drives clock loads in clock columns X2, X3, X4, X5, X6, X7, X8, and X9. The clock root X7Y4 on the left results in a lower Fmax because two additional fabric clock regions are traversed in the horizontal direction for the maximum clock extent compared to the more optimal clock root X5Y4 in the left picture. The USER_CLOCK_ROOT property can be used to assign the clock root in the most central vertical NoC column:

set_property USER_CLOCK_ROOT X5Y4 [get_nets -of [get_pins BUFGCE_inst/O]]
Figure 1. Central Clock Root Results Comparison