Boundary Clock Nets - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

After the first implementation, boundary clock net tracks are locked. The partition pin locations (PPLOCs) on the boundary clock nets are distributed to all clock regions covered by the reconfigurable partition (RP) Pblock.

The clock root of the boundary clock net can be placed anywhere in the device, because the boundary clock net can drive both static and RP loads. AMD recommends using the USER_CLOCK_ROOT constraint on the boundary clock net to manually constrain the CLOCK_ROOT location due to the following:

  • If the loads of the boundary clock are located mainly in the static region, the clock root might be placed in the static region.
  • If the first implementation uses training logic in the RP Pblock, boundary clock nets might be locked down after the first implementation with an off-center clock root location.
  • Because the boundary clock net is distributed to all clock regions covered by the RP Pblock, the clock insertion delay for the boundary clock is relatively high compared with the internal RM clock nets.
    Note: Versal devices with SSI technology have stricter requirements for the clock root. For clock nets spanning multiple super logic regions (SLRs), the clock root is generally placed at the top of an SLR in the middle of the device to balance the clock tree. Therefore, AMD recommends that you avoid using boundary clocks for timing critical paths in your design that require low clock insertion delays.