Avoiding Local Clocks - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
Release Date
2023.2 English

Local clocks are clock nets routed with regular fabric resources instead of dedicated global clocking resources. In most cases, the Vivado synthesis and Vivado logic optimization tools insert clock buffers where mandated by the architecture or for clock nets with more than 30 clock loads. Local clocks typically occur when:

  • A global clock is divided by a counter implemented with fabric logic
  • Clock gating conversion is not able to remove all LUTs from the clock path

In general, avoid using local clocks. Local clocks introduce several challenges to the implementation tools:

  • Unpredictable clock skew, leading to difficult timing closure
  • Increase of low to medium fanout nets that are processed with special care by the router, leading to potential routability problems
    Tip: If local clocks introduce timing QoR problems, try floorplanning the clock driver and loads to a small area using a Pblock. Use report_clock_utilization to identify the location of the local clocks, review the clock placement, and decide on how to reduce their number or impact.
Versal devices provide the BUFG_FABRIC cell that can be used to route a net from regular fabric resources onto the dedicated global clocking resources. BUFG_FABRIC sites exist throughout the device in NoC columns and are used to route high fanout nets, such as resets and clock enables on global clocking resources.
The BUFG_FABRIC cell is not intended for clock nets to access the global clocking resources. If you have a local clock that requires the use of the global clock network and direct access to the global clocking resources is not possible, the BUFG_FABRIC can be used to route the local clock onto the global clock network. The resulting clock will have suboptimal timing characteristics when compared to a clock that has direct access to the global clocking resources.