Avoid GT Column When Clock Crosses SLRs - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

A clock route through the GT column that crosses the SLR boundary will result in a lower supported Fmax compared to the same clock route and extent through the vertical NoC column. For clock networks that extend across the SLR boundary, performance can be improved by choosing a clock root in one of the vertical NoC columns instead of the GT column. In the example below, a BUFG_GT in clock region X9Y4 drives clock loads in clock columns X6, X7, X8, and X9. The clock root X9Y4 on the left results in a lower Fmax because the vertical distribution crosses the SLR boundary in the GT clocking column. The clock root X7Y4 on the left improves Fmax because it crosses the SLR boundary in the vertical NoC column. The USER_CLOCK_ROOT property can be used to assign the clock root in the vertical NoC column:

set_property USER_CLOCK_ROOT X7Y4 [get_nets -of [get_pins BUFG_GT_inst/O]]
Figure 1. Clock Root in Vertical NoC Column versus GT Column