About This Guide - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
Release Date
2023.2 English

This guide includes high-level information, design guidelines, and design decision trade-offs for the following topics:

Design Planning
Provides information on planning your design to maximize the Versal architecture, including planning for key IP blocks, for DFX designs, and for the different design flows.
Design Creation with Block Designs
Provides guidelines for creating block designs that include GT, CIPS, NoC, and other IP as well as custom-packaged IP and RTL.
Design Creation with RTL
Provides best practices for creating RTL modules that are needed for higher performance or special functionality that is not available in the IP catalog.
Design Creation with Vitis HLS
Provides an overview of creating a design with Vitis HLS as well as recommended methodology, including defining interfaces and using the Vitis kernel flow.
I/O Planning Design Flows
Provides information on different I/O planning flows and recommendations for assigning signals to specific pins to streamline the dataflow through the device and meet high performance requirements.
Design Constraints
Provides recommendations for creating proper timing, power, and physical constraints as well as specifying additional constraints, attributes, and other elements used during synthesis and implementation.
Design Implementation
Provides best practices for synthesizing and implementing the design.
Embedded Platform Creation for the Vitis Environment
Provides high-level information on creating an embedded platform, including mapping functionality to the platform and subsystem.