Vivado Design Suite - 2023.2 English

Versal Adaptive SoC System Software Developers Guide (UG1304)

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2023.2 English

The AMD Vivado™ Design Suite contains tools that are encapsulated in the Vivado IDE. The IDE provides an intuitive GUI with powerful features.

The tools deliver a SoC-strength, IP- and system-centric, development environment built exclusively by AMD to address the productivity bottlenecks in system-level integration and implementation.

All commands and command options in the Vivado Design Suite use the native tool command language (Tcl) format, which can run on both, the Vivado IDE or the Vivado Design Suite Tcl shell. Analysis and constraint assignment is enabled throughout the design process. For example, you can run timing or power estimations after synthesis, placement, or routing. As the database is accessible through Tcl, changes to constraints, design configuration, or tool settings happen in real time, often without forcing re-implementation.

The Vivado IDE uses a concept of opening designs in memory. Opening a design loads the design (an ASCII file defining the components and their connections) at that particular stage of the design flow, assigns the constraints to the design, and applies the design to the target device. This provides the ability to visualize and interact with the design at each design stage.

You can improve design performance and ease of use through the features delivered by the Vivado Design Suite, including:

  • The control, interfaces, and processing system IP (CIPS) configuration within IP integrator with graphical user interfaces to let you create and modify the CIPS within the IP integrator block design.
  • Register transfer level (RTL) design in VHDL, Verilog, and SystemVerilog
  • Quick integration and configuration of IP cores from the AMD IP catalog to create block designs through the Vivado IP integrator
  • Vivado synthesis
  • C-based sources in C, C++, and SystemC
  • Vivado implementation for place and route
  • Vivado serial I/O and logic analyzer for debugging
  • Vivado power analysis
  • Synopsys design constraints (SDC)-based Xilinx design constraints (XDC) for timing constraints entry
  • Static timing analysis
  • Flexible floorplanning
  • Detailed placement and routing modification
  • Vivado Tcl Store, which you can use to add to and modify the capabilities in the Vivado tool

You can download the Vivado Design Suite from Vivado Design Suite – ML Editions.