Versal Devices Using SSI Technology - 2023.2 English

Versal Adaptive SoC System Software Developers Guide (UG1304)

Document ID
Release Date
2023.2 English

Versal devices built using stacked silicon interconnect (SSI) technology include multiple SLRs that are connected to one another via NoC, PL Laguna, or dedicated PMC-to-PMC sidebands, all routed through an interposer layer.

Each SLR includes its own dedicated PMC block that can run firmware and a PL region. Secondary SLRs do not have a PS region and AI Engines. Configurations in these secondary SLRs go through their local PMC. The PMC in the primary SLR is responsible for accessing the boot device and runs the main firmware which handles the transfer of firmware and programming data for the other SLRs to their corresponding PMCs via the NoC.