Error Events - 2023.2 English

Versal Adaptive SoC System Software Developers Guide (UG1304)

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2023.2 English

For safety applications:

  • You should enable any of the supported error actions through a CDO command at PMC/PSM EAM level. Refer to the Configuration of EAM errors through a CDO section for an example. Also, you should enable the corresponding errors at the block level such as NoC, DDR memory, or XMPU/XPPU.
  • If you are using Arm Cortex-R5F and Cortex-A72 applications, you should enable notifications for error interrupts by configuring the Error Management action as interrupt to R5/A72. Refer to the Register Notifier for EM Events section. When configured, it checks the source error status and takes any appropriate action.

For a complete list of the available error events, refer to the Versal Adaptive SoC Technical Reference Manual (AM011).