Application Processing Unit - 2023.2 English

Versal Adaptive SoC System Software Developers Guide (UG1304)

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2023.2 English

Versal Devices

The application processing unit (APU) consists of an Arm Cortex-A72 processor, L1/L2 caches, and related functionality. The Cortex-A72 cores and caches are part of the Arm processor MPCore IP, with integrated L1 and L2 caches.

Versal devices have a dual-core Cortex-A72 with 1 MB L2 cache. The Cortex-A72 cores implement Armv8 64-bit architecture with GIC-500 interrupt controller.

The APU includes the following features:

  • Dual-core Cortex-A72 core class with 1 MB L2 with error correction code (ECC). The L1 caches include I-cache of 48 KB in size and for I-cache and D-cache of 32 KB in size. L1 caches include error correction code (ECC).
  • Per core power-gating support
  • TrustZone support