XPIO - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

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2023.2 English

The XPIO in Versal adaptive SoCs are similar to the high-speed I/O (HPIO) in the AMD UltraScaleā„¢ architecture. However, the XPIO are located at the bottom and/or top periphery of the device, unlike the I/O columnar layout in previous devices. The XPIO provide XPHY logic that is similar to UltraScale device native mode. The XPHY logic encapsulates calibrated delays along with serialization and deserialization logic for six single-ended I/O ports known as nibble. Each XPIO bank contains nine XPHY logic sites and supports up to 54 single-ended I/O ports. The XPHY logic is used for the integrated DDR memory controller, soft memory controllers, and custom high-performance I/O interfaces. For more information on the XPIO, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).