UltraRAM Primitives - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
Release Date
2023.2 English

Following is the UltraRAM primitive in Versal adaptive SoCs. To force Vivado synthesis to infer the UltraRAM, set the RAM_STYLE = "ultra" attribute on the RAM.

Note: Like UltraScale devices, the UltraRAM for Versal adaptive SoCs includes only one clock.
Primitive Supported Aspect Ratios Supported Mode
URAM288E5 4Kx72




Dual port

Single port

Extra Registers

In addition to the optional output registers, the UltraRAM supports input registers on the data lines. As with block RAMs, you can reset the optional registers either with synchronous or asynchronous reset signals.

RAM Initialization

In Versal adaptive SoCs, the UltraRAMs can be initialized to a non-zero value. Initialize the UltraRAMs using the INIT_xx attribute on the RAM as follows:

  • Verilog: Use the readmemh command.
  • VHDL: Set up a function to read an external file in VHDL.

For details, see the Vivado Design Suite User Guide: Synthesis (UG901).

Byte Write Enables

The UltraRAM also supports byte write enable operations. As with block RAMs, the bytes can either be 8 bits or 9 bits using the extra parity bit. However, when using byte write with Versal adaptive SoCs, read operations are ignored during writing. Therefore, only the NO_CHANGE mode is supported when describing UltraRAMs with byte write.

Asymmetric UltraRAMs

Versal adaptive SoC UltraRAMs support asymmetric aspect ratios. For examples on how to code asymmetric RAMs, see this link in the Vivado Design Suite User Guide: Synthesis (UG901).

XPM Inference

UltraRAMs can also be inferred using XPMs. The advantage of using this approach is that XPMs always have the correct coding style for any type of RAM needed. For more information on XPMs, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895).