System Architecture - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
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2023.2 English

AMD Versal™ devices are divided into series that are targeted to different applications and markets. Some components are consistent between series and some vary either in availability or features. A few of the major resources include:

  • AI Engine
  • Programmable logic (PL)
  • Network on chip (NoC)
  • High-speed I/O (XPIO)
  • Integrated memory controllers (DDR memory controller)
  • High bandwidth memory (HBM)
  • Processing system (PS)
  • Platform management controller (PMC)
  • Integrated block for PCIe® with DMA and cache coherent interconnect (CPM)
  • Transceivers (GT)
  • High-speed debug port (HSDP)
  • High-speed connectivity and encryption integrated IP

The following table shows several features that vary between series. If a resource is present in a device listed in the column header, it is of the type listed in the table. Not all devices include all resources, see the Versal Architecture and Product Data Sheet: Overview (DS950) for more detail and device-specific information.

Table 1. Versal Device by Series
Series AI Edge AI Core Prime Premium HBM
Devices VE1xxx VE2xxx VC1xxx VC2xxx VM1xxx VM2xxx VP10xx VP1xxx VP2xxx All
AI Engine AIE AIE-ML AIE AIE-ML - - - - AIE -
Processing System PS PS PS PS PS PS PS PS PS PS
GTM - - - - - 58G 112G 112G 112G 112G
CPM Gen4x16 Gen4x16 Gen4x16 Gen5x8 Gen4x16 Gen5x8 Gen4x4 Gen5x8 Gen5x8 Gen5x8
PCIe Gen4x8 Gen4x8 Gen4x8 Gen5x4 Gen4x8 Gen5x4 Gen4x8 Gen5x4 Gen5x4 Gen5x4
Multirate Ethernet MAC 40G 100G 100G 100G 100G 100G 100G 100G 100G 100G
600G Ethernet MAC - - - - - - 600G 600G 600G 600G
600G Interlaken - - - - - - 600G 600G 600G 600G
400G High-Speed Crypto - - - - - - 400G 400G 400G 400G
HBM - - - - - - - - - Yes
VDU - Yes - Yes - - - - - -

Versal device applications can exploit the capabilities of each of these resources. To create or migrate a design to a Versal device, you must identify which resources best satisfy the different needs of the application and partition the application across those resources.

The following figure shows the layout of the Versal device.

Figure 1. Versal Device Layout

The following sections provide a summary of the blocks that comprise the Versal architecture. For detailed information on these blocks, see the Versal Architecture and Product Data Sheet: Overview (DS950).