The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 10/25/2023 Version 2023.2 | |
| About This Guide | Added XTP751 reference. |
| AI Engine | Added AM020 reference. |
| APU | Added Arm TrustZone to table. |
| System Design Types | Added AIE-ML link to table. |
| Developing and Verifying the AI Engine Graph | Added AI Engine graph test description. |
| Testing the Adaptable Subsystem Using a Standard AMD Platform | Updated title. |
| Integrating the Adaptable Subsystem with the Custom Platform | Updated section. |
| AI Engine Simulation | Updated input_plio
statement. |
| Security | Added Asymmetric Authentication in table. |
| Boot and Configuration | Updated SelectMAP note in the Boot Mode Comparison table. |
| PL Configuration and JTAG | Removed AM011 link. |
| 05/10/2023 Version 2023.1 | |
| Document title | Changed title to Versal Adaptive SoC Design Guide (UG1273). |
| System Architecture | Added Versal Device by Series table. |
| AI Engine | Added AIE-ML. |
| HBM | Added new section. |
| System Design Types | Added HBM description. |
| Design Flows | Added HBM description. |
| Traditional Design Flow for Hardware-Only Systems | Added HBM description. |
| Traditional Design Flow for Embedded Systems | Added HBM description. |
| Platform-Based Design Flows | Added AI Edge. |
| Simulation Flows | Added HBM in Supported Simulation Models for Versal Device Blocks table. |
| HBM | Added new section. |