Platform-Based Design Flows - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

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2023.2 English

In the platform-based design flow, the hardware design is conceptually divided in two distinct elements: the platform and the processing system. The platform contains essential Versal IP blocks (including CIPS, NoC, AI Engine, and Clocking Wizard) and board interface IP blocks (including high-speed I/Os and memory controllers). The processing system contains the application-specific part of the system and can be composed of both programmable logic and AI Engine blocks. The platform is considered extensible, because the platform does not contain the entirety of the programmable logic content. Instead, the platform is extended by the addition of the processing system.

Following are the main steps in this flow. The first three steps can be completed in parallel. You can update the AI Engine program independently after the fixed hardware platform is finalized.

  1. Develop the hardware platform using the Vivado IP integrator and RTL code.
  2. Develop the AI Engine graph and kernels using the Vitis tools.
    Note: The AI Engine is only available if you are using the Versal AI Core and AI Edge series or Versal Premium with AI Engine.
  3. Develop the PL kernels using the Vitis tools (C++ kernels) or the Vivado tools (RTL kernels).
  4. Assemble the AI Engine program and the PL kernels to form the processing system and integrate the processing system with the platform using the Vitis linker to create a fixed hardware design.
  5. Implement and perform design closure on the fixed hardware design using the Vivado tools.
  6. Develop the software application on top of the fixed hardware design using the Vitis embedded software development flow.
Note: The Vivado IP integrator is supported in Project Mode only.
Important: This is the only flow that supports programming of the AI Engine cores and is therefore required for Versal AI Core, AI Edge, or Premium devices.
Tip: AMD provides off-the-shelf platforms for Versal adaptive SoC evaluation kits, such as the VCK190.