Hardware Testing - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

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2023.2 English

Using the Vitis design flow, the same subsystem that can be simulated using the hardware emulation flow can be implemented and deployed on hardware. When targeting a hardware board, the Vitis linker sends the PL region of the system through Vivado synthesis as well as place and route.

By testing in hardware, you can get early feedback on timing closure and resource utilization. Most importantly, you can run the subsystem at speed on hardware for more realistic performance results as follows:

  • More accurate execution profile of control code running on the PS
  • More realistic I/O patterns, resulting in more realistic exercising of stalls and back pressure
  • Discovery of corner cases that cannot be reached in the slower hardware emulation runs

Using a combination of compile-time and runtime options, the Vitis environment design flow allows you to select which information to profile or trace. When the system is run on the hardware board, this information is automatically collected by the system, and you can use the Vitis Analyzer tool to view and analyze this data.

For more information on how to assemble and verify the subsystem on hardware, see the Implementation section and System Bring Up and Validation section of the Versal Adaptive SoC Design Process Documentation: System Integration and Validation.