Hardware Emulation - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

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2023.2 English

Hardware emulation simulates a complete Versal adaptive SoC system composed of the AI Engine, PS, and PL. Using the Vitis software platform, you can integrate blocks and functions targeting all three compute domains. The Vitis linker automatically generates a complete co-simulation setup involving RTL, SystemC, and QEMU models:

  • Embedded software code running on the PS is emulated using QEMU.
  • Code running on the AI Engines is emulated using the SystemC AI Engine simulator.
  • User PL kernels are simulated as RTL code.
  • IP blocks in the hardware platform are simulated either as RTL or SystemC TLM, based on the types of models available or selected.

As a result, the abstraction of the Vitis hardware emulation is very close to but not fully cycle-accurate. Some details of the Versal adaptive SoC platform are abstracted with TLM models for simulation speed purposes.

The scope of the Vitis hardware emulation also defines its purpose. Hardware emulation allows you to simulate the entire design and test the interactions between the PL, PS, and AI Engine prior to implementation. Because hardware emulation provides full debug visibility into all aspects of the application, it is easier to debug complex problems in this environment than in real hardware.

Hardware emulation is available through the Vitis unified software platform. For more information, see the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393) and the AI Engine Tools and Flows User Guide (UG1076).

You can use AXI traffic generators as an to alternative to using file-based inputs and outputs. In contrast to file-based inputs and outputs that are static and limited, AXI traffic generators are a dynamic way to produce and consume data. For more information, see the AXIS External Traffic Generator Feature Tutorial.

Using AXI traffic generators offers the following advantages:

  • Allows you to reuse the same simulation set used during AI Engine simulation
  • Allows you to abstract some of the blocks in your system with traffic generators, which are faster to simulate
Note: Hardware emulation is only possible in the platform-based design flow.