Developing and Verifying the AI Engine Graph - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

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2023.2 English

An AI Engine program consists of a dataflow graph specification written in C++, which comprises nodes and edges. Nodes represent compute functions (known as kernels), and edges represent data connections. The AI Engine graph specification is compiled using the Vitis aiecompiler and simulated with the Vitis aiesimulator.

AMD recommends gradually refining and testing the graph, slowly progressing from scalar to vectorized operations. This allows you to set up your system (for example, build scripts, functional correctness, etc.) without having to do low-level AI Engine-specific coding.

The graph is tested with a user-written test bench that drives and manages the graph using the graph application programming interfaces (APIs). Following are the methods for getting data into and out of a graph:

  • Runtime parameters (RTPs) are programmable registers used to exchange values between the PS application and the AI Engine kernels.
  • GMIOs provide a direct connection from the AI Engine to global memory via the horizontal NoC.
  • PLIOs provide a direct streaming connection between AI Engine kernels and PL blocks.

The test bench can consist of basic file I/O-operations or more powerful traffic-generators written in Python, C/C++, or HDL to get data into and out of the AI Engine graph.

Important: It is important to monitor performance results and meet performance goals at this stage, because the system performance will not improve as you progress through the development stages. However, meeting performance in the aiesimulator at this early stage in the design is not indicative of the final system performance, because the aiesimulator simulates I/O traffic assuming best case operating conditions.

After testing the AI Engine graph using simulation, AMD recommends testing the graph on hardware. To facilitate the testing of AI Engine graphs on the VCK190, AMD provides a ready-to-use test harness. This test harness is designed to provide a simple and natural transition from the AI Engine simulation environment to testing on hardware. With the test harness, AI Engine graphs running in simulation can be taken to hardware within a few minutes and with only a few minor modifications. For more information on the AI Engine test harness, see the AIE Test Harness available from the AMD GitHub repository.

For more information on how to develop and simulate AI Engine graphs and kernels, see the Versal Adaptive SoC Design Process Documentation: AI Engine Development.