DDR Memory Controller for DDR4, LPDDR4, and LPDDR4X - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

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2023.2 English

The DDR memory controller is a high-efficiency, low-latency integrated DDR memory controller for a variety of applications, including general purpose central processing units (CPUs) as well as other traditional field programmable gate array (FPGA) applications, such as video or network buffering.

The controller operates at half the DRAM clock frequency and supports DDR4, LPDDR4, and LPDDR4X standards up to 4266 Mbps. The controller can be configured as a single DDR memory interface with data widths of 16, 32, and 64 bits, plus an extra 8 check bits when error-correction code (ECC) is enabled. The controller can also be configured as 2 independent or interleaved DDR interfaces of 16 or 32 data bits each. The controller supports x4, x8, and x16 DDR4 and x32 LPDDR4 components, small outline dual in-line memory modules (SODIMMs), unbuffered DIMMs (UDIMMs), registered DIMMs (RDIMMs), and load-reduced DIMMs (LRDIMMs). The DDR memory controller is accessed through the NoC. The optimal combination of memory interfaces with various width, type, and speed can be identified by using the Versal Adaptive SoC External Memory Pre-Planning Tool (XTP667). For additional information, see the Memory Pinouts Tutorial available from the AMD GitHub repository.

In Versal adaptive SoC, the DDR memory controller is a system-wide, shared resource. It is shared between the PS and PL via the device-wide, high-performance NoC interface. The NoC IP core can be configured to include one or more integrated DDR memory controllers. If two or four DDR memory controllers are selected, the DDR memory controllers are grouped to form a single interleaved memory. In interleaved mode, the application views the participating DDR memory controllers as a single unified block of memory. The NoC supports interleaving across two or four DDR memory controllers by automatically dividing AXI requests into interleaved, block-sized subrequests and alternately sending the subrequests to each of the participating DDR memory controllers.

Important: You must use the NoC to connect between the PL, PS, CPM, or AI Engine and the DDR memory controller.

For more information on the DDR memory controller, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

Note: Versal adaptive SoC also supports soft memory controllers in the PL fabric, similar to previous device families.