CIPS IP Core - 2023.2 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
Release Date
2023.2 English

The CIPS IP allows you to configure the following:

  • Device clocking to the PMC, PS, NoC, and optionally, PL
  • PMC flash controllers, peripherals, and their associated multiplexed I/O (MIO)
  • PS peripherals and their associated I/O
  • PS-PL interrupts and cross-triggering
  • CPM (the integrated block for PCIe┬« with DMA and cache coherent interconnect)
  • PS and CPM AXI interfaces to NoC and PL
  • System Monitor supply and temperature monitoring and alarms
  • HSDP for high-speed debugging

For more information, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).