Versal (Segmented Configuration Flow) - 2023.2 English - UG1144

Prerequisites

Versal flat design(xsa) contains boot pdi which includes Versal cips + NOC + DDR, and pld pdi, which has PL IPs

Build Steps

This section helps to build and boot segmented configuration design flow for Versal platforms.

1. Source the PetaLinux tool

   source /opt/petalinux/petalinux-v<petalinux-version>-final/settings.sh

2. Create a Versal template project or BSP project

   petalinux-create -t project -n versal-seg-flow --template versal
    petalinux-create -t project -s <bsp path> -n versal-seg-flow

3. Go to the project

   cd versal-seg-flow

4. Configure the project with flat xsa if you create project in template flow

    petalinux-config --get-hw-description <flat.xsa>

5. Enable FPGA manager, select FPGA Manager → [*] Fpga Manager.
   Note: The PetaLinux FPGA manager configuration performs the following:

   • fpga-overlay Machine features
   • Enables the required kernel configs to load the fpgamanager driver
6. Create the pl application to pack the pl pdi and the pl ips dtbo into rootfs command:

   petalinux-create -t apps --template dfx_dtg_versal_full -n pl-app --
    enable --srcuri "<path>/rprm.xsa>"

   The previous command generates and packages the rm dtbo, pl pdi files into the rootfs(/lib/firmware/xilinx/<pl-app>)
7. To build the application, use the following command. The following command generates the rootfs containing the rprm, dtbo, and respective pdi files:

   petalinux-build
   petalinux-build -c rootfs

   To build only the application:

   petalinux-build -c <pl-app>

8. To boot target with PS generate the boot.bin using the following command:

   petalinux-package --boot --u-boot (It will pick *_soc.pdi) and packs as part of the boot.bin

Boot Steps

Once the base target is up, run the following command:

fpgautil -o /lib/firmware/can interface/pl.dtbo -b /lib/firmware/xilinx/pl-app/hw_description_pld.pdi