FPGA Manager Configuration and Usage for Zynq 7000 Devices and Zynq UltraScale+ MPSoC - 2023.2 English

PetaLinux Tools Documentation: Reference Guide (UG1144)

Document ID
Release Date
2023.2 English
The FPGA manager provides an interface to Linux for configuring the programmable logic (PL). It packs the dtbos and bitstreams/pdi files into the /lib/firmware/xilinx directory in the root file system.

After creating a PetaLinux project, follow these steps to build the FPGA manager support:

  1. Go to cd <plnx-proj-root>.
  2. In the petalinux-config command, select FPGA Manager > [*] Fpga Manager.
    Note: The PetaLinux FPGA manager configuration performs the following:
    1. Generates the pl.dtsi nodes as a dt overlay (dtbo).
    2. Packs the dtbos and bitstreams in the .bin format or pdi into the /lib/firmware/xilinx/base directory in the root file system.
  3. You can use the petalinux-create command to add the PL xsa files into the PetaLinux project. The following command creates the fpgamanager_dtg app with the xsa file to generate the dtsi and bit files.
    petalinux-create -t apps --template fpgamanager_dtg -n can-interface --srcuri <path-to-xsa>/system.xsa --enable
    INFO: Create apps: can-interface
    INFO: Copying source urls into the project directory
    INFO: New apps successfully created in <plnx-proj-root>/project-spec/meta-user/recipes-apps/can-interface
    INFO: Enabling created component...
    INFO: Sourcing build environment
    INFO: Silentconfig rootfs
    INFO: can-interface has been enabled
    Note: For each XSA, create a separate app using the previous command. FPGA manager should be enabled in petalinux-config for both fpgamanager and fpgamanager_dtg template apps.
  4. Run petalinux-build.

Example loading full bitstream on target:

root@xilinx-zcu102:~# fpgautil -o /lib/firmware/xilinx/base/pl.dtbo -b 

Time taken to load DTBO is 239.000000 milli seconds. DTBO loaded through ZynqMP FPGA manager successfully.

Loading a full bitstream through sysfs – loading bitstream only:

root@xilinx-zcu102-2023_1:~# fpgautil  -b /mnt/design_1_wrapper.bit.bin

Time taken to load BIN is 213.000000 milli seconds. BIN FILE loaded through zynqMP FPGA manager successfully.

See help section for more option: root@xilinx-zcu102-2020_1:~# fpgautil -h. For more information, see https://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming.

Figure 1. FPGA Manager