This section helps to build and boot DFX (single slot) design for Versal platform.
Note: If DFX applications(rm.xsa) have any memory mapped PL
IPs,
only then use fpgamanager_dtg_dfx template. If not, you can use --template install
to pack only pdi as part of rootfs.
- Source the PetaLinux tool.
source /opt/petalinux/petalinux-v<petalinux-version>/settings.sh - Create a Versal template project or
bsp
project
petalinux-create -t project -n versal-dfx --template versalpetalinux-create -t project -s <bsp path> -n versal-dfx - Go to the
project
cd versal-dfx - Configure the project with
static.xsa/base.xsa
petalinux-config --get-hw-description <base.xsa/static.xsa> - Enable FPGA manager using the following
command:
petalinux-config -> FPGA MANAGER - Create the static/base application using the following command from
static/base
xsa:
petalinux-create -t apps --template fpgamanager_dtg -n <static-app> --enable --srcuri "<static xsa>"The previous command creates and packages the static dtbo and pdi files into the rootfs (/lib/firmware/xilinx/) using fpgamanager_dtg template.
- Create the partial application to configure the partial region using
the rm xsa in the following command. You should point static pl app name as
--static-pncommand line option to define the relation between base and partial.petalinux-create -t apps --template fpgamanager_dtg_dfx -n <rm-app> --enable --srcuri <rm.xsa>" --static-pn <static-app>This command generates and packages the rm dtbo, pdi files into the rootfs (/lib/firmware/xilinx/<static-app>/<rm-app>).
- Execute
petalinux-buildThe command generates the rootfs containing both static and rprm dtbos, and respective pdi files as mentioned in the step 5 and step 6.
Once the base boot images ready with the previous step, if you want to build only DFX apps, use the commands mentioned in step 8.
- Execute the following
command:
petalinux-build -c <static-app> petalinux-build -c <rm-app> in below path you will see with the below names. in <TMPDIR>/deploy/rpm you will see <static-app>.rpm and <rm-app>.rpm
Note: The pdi's in the design should have
i*_partial.pdi in the xsa files to avoid an error.Note: In DFX use case, you can use the static xsa to
create the Versal boot firmware images so static pdi
is packaged as part of BOOT.BIN.
Boot Steps
Up the target with previous built images using any of the boot methods in the documentation. Once the target is up.vck190-dfx:/home/petalinux# fpgautil -o /lib/firmware/xilinx/<static-app>/<static-app>.dtbo
[ 71.571728] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/external-fpga-config
[ 71.582142] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay0
[ 71.592010] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR0
[ 71.601854] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay2
[ 71.611688] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_SIHA_Manager_0
[ 71.623169] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_axi_gpio_0
[ 71.634302] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_axi_intc_0
[ 71.645435] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_clk_gen_clk_wizard_0
[ 71.660647] of-fpga-region fpga:fpga-PR0: FPGA Region probed
[ 71.667512] irq-xilinx: mismatch in kind-of-intr param
[ 71.672705] irq-xilinx: /axi/interrupt-controller@a4060000: num_irq=32, sw_irq=0, edge=0xffffffff
vck190-dfx:/home/petalinux#
vck190-dfx:/home/petalinux# fpgautil -b /lib/firmware/xilinx/<static-app>;/rp0/<rprm-app>/<rprm-app>.pdi -o /lib/firmware/xilinx/<static-app>/rp0/<rprm-app>/<rprm-app>.dtbo -f Partial -n PR0
[ 142.795102] fpga_manager fpga0: writing opendfx-rp0-aes128.pdi to Xilinx Versal FPGA Manager
[152814.496]Loading PDI from DDR
[152814.609]Monolithic/Master Device
[152817.904]3.383 ms: PDI initialization time
[152821.876]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700000
[152827.520]---Loading Partition#: 0x0, Id: 0x103
[152831.949] 0.046 ms for Partition#: 0x0, Size: 28560 Bytes
[152837.180]---Loading Partition#: 0x1, Id: 0x105
[152841.567] 0.005 ms for Partition#: 0x1, Size: 32 Bytes
[152846.582]---Loading Partition#: 0x2, Id: 0x205
[152851.076] 0.112 ms for Partition#: 0x2, Size: 2064 Bytes
[152856.156]---Loading Partition#: 0x3, Id: 0x203
[152860.565] 0.027 ms for Partition#: 0x3, Size: 544 Bytes
[152865.643]---Loading Partition#: 0x4, Id: 0x303
[152875.331] 5.304 ms for Partition#: 0x4, Size: 3238160 Bytes
[152878.011]---Loading Partition#: 0x5, Id: 0x305
[152882.801] 0.406 ms for Partition#: 0x5, Size: 7296 Bytes
[152887.586]---Loading Partition#: 0x6, Id: 0x403
[152892.020] 0.051 ms for Partition#: 0x6, Size: 49312 Bytes
[152897.246]---Loading Partition#: 0x7, Id: 0x405
[152901.633] 0.005 ms for Partition#: 0x7, Size: 32 Bytes
[152906.697]Subsystem PDI Load: Done
[ 142.904337] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay0RP_0_AES128_inst_0
[ 142.918020] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay2_RP_0_AES128_inst_0
[ 142.929504] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/RP_0_AccelConfig_0
[ 142.940202] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_RP_0_AES128_inst_00
[ 142.951768] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/RP_0_axi_gpio_0
[ 142.962208] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/RP_0_rm_comm_box_0
[ 142.975851] gpio-xilinx 20100010000.gpio: #gpio-cells mismatch
[ 142.981709] gpio-xilinx: probe of 20100010000.gpio failed with error -22
Time taken to load BIN is 196.000000 Milli Seconds
BIN FILE loaded through FPGA manager successfully
vck190-dfx:/home/petalinux#