After authenticating and/or decrypting, the FSBL is loaded into OCM and handed off by the CSU bootROM. First Stage Boot Loader configures the FPGA with a bitstream (if it exists) and loads the Standalone (SA) Image or Second Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to RAM(DDR/TCM/OCM). It takes the Cortex-R5F-0/R5F-1 processor or the Cortex-A53 processor unit out of reset. It supports multiple partitions. Each partition can be a code image or a bitstream. Each of these partitions, if required, will be authenticated and/or decrypted.
Note: If you are creating a custom FSBL, you should be aware that the OCM size is 256 KB and is
available to CSU bootROM. The FSBL size is close to 170 KB and it would fit in the OCM.
While using the USB boot mode, you should make sure that the PMU firmware is loaded by
the FSBL and not by the CSU bootROM. This is because the size of boot.bin loaded by the
CSU bootROM should be less than 256 KB.
Note: Users can load bitstream from OCM for non-encrypted cases even if DDR is
present in the design. By default, the
FSBL_PL_LOAD_FROM_OCM_EXCLUDE_VAL value is set to 0 in
xfsbl_config.h, making the bitstream copy and load from DDR in
the non-encrypted cases. By setting the
FSBL_PL_LOAD_FROM_OCM_EXCLUDE_VAL value to 1, the user can ensure that
bitstream is loaded from OCM in chunks and not from DDR. Also, if DDR is not present in
the design, the bitstream is loaded from OCM irrespective of the
FSBL_PL_LOAD_FROM_OCM_EXCLUDE_VAL value.