When verbose (
-v) mode of aiecompiler is enabled, the Vitis IDE generates a summary table to show the pipeline results,
with the following information: -
TILE: The AI Engine Tile coordinates of the kernel. -
MIN II: The minimum II that loop may try to achieve due to resources limitation. -
ACTUAL II: The actual II that the loop achieves. -
SOURCE: The loop source code.
An example loop II table is as follows:
Figure 1. Loop II
