Vitis Integrated Design Environment
The AMD Vitis™ integrated design environment (IDE) can be used to target system programming of AMD devices including, AMD Versal™ devices with AI Engine array. The following features are available in the tool.
- An optimizing C/C++ compiler that compiles the kernels and graph code making all of the necessary connections, placements, and checks to ensure proper functioning on the device.
- A cycle approximate simulator, accelerated functional simulator, and profiling tools.
- A debugging environment that works in both simulation and hardware environments.
New Vitis Integrated Design Environment
This new IDE replaces the standalone Vitis Analyzer classic tool. This IDE is used to view compilation and simulation reports, and analyze output files generated by the AI Engine compiler. In addition, it can also be used to view and analyze system application reports. More information about this design environment and how it can be used to create components is found in Introduction to the Vitis Unified IDE in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
vitis_analyzer
--classic
.Vitis Command Line Tools
Command line tools are available to build, simulate, and generate output files and reports. Command line outputs which are generated by the IDE are captured to facilitate subsequent integration into customer build environments. The unified Vitis IDE is also available for report viewing and analysis of the output files and reports generated by the command line tools.
New Vitis Unified Command Line Interface
For information about the new Vitis unified command line interface, see the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
Vitis Model Composer
- Import AI Engine kernels, graphs, HLS kernels, and RTL based blocks into one Simulink® design for fast co-simulation.
- From the Simulink library browser, drag and drop optimized AI Engine functions from Vitis Libraries such as Finite Impulse Response (FIR) and FFT filters into the design.
- Verify the design using stimulus generated in MATLAB or Simulink, visualize the results, and compare the results with golden reference. Generate graph code and test vectors.
- Assemble imported and block library code to feed into downstream tools.