Memory Stall Analysis - 2023.2 English

AI Engine Tools and Flows User Guide (UG1076)

Document ID

UG1076

Release Date

2023-12-04

Version

2023.2 English

AI Engine can perform several vector load or store operations per cycle. However, for the load or store operations to be executed in parallel, they must target different memory banks. Memory stall happens when multiple access on the same bank of memory on the same cycle.

The kinds of memory include window buffer and DMA FIFO between kernels, RTP buffer, and system memory. System memory includes kernel synchronization information in the first 32 bytes, stack, and heap. Static variables are in the heap and function control logics are in the stack. System memory occupies continuous memory banks. Tool can automatically or manually place window buffer, RTP buffer, DMA FIFO, and system memory on specific banks. To alleviate memory stalls between these memories, try to place them into separate banks if possible. But memory stall can still happen between these kinds of memories if separate banks cannot be found for all the memories, or multiple accesses are happening on the same memory.

In general, the compiler tries to schedule many memory accesses in the same cycle when possible, but there are some exceptions. Memory accesses coming from the same pointer are scheduled on different cycles. If the compiler schedules the operations on multiple variables or pointers in the same cycle, memory bank conflicts can occur. Each memory bank has its arbitrator to arbitrate between all requests, and the arbitration is round-robin. After every request has been addressed, the memory stall is released.

From Performance Metrics analysis, you can identify if the memory stall needs to be analyzed.

Select the Trace view.
Select the Memory Stalls table.
Figure 1. Memory Stall in the Trace View

The stall is named as MS_<NUM>. The number is increased by time. Each stall has the following associated information.

NAME

The memory stall id. The earlier the stall happens, the smaller the number. The number is unique across all types of stall.

Stalled Tile

The AI Engine tile where the stalled kernel is located.

Stalled Kernel

The kernel that is stalled. It is named <Kernel_function_name>.<Schedule_ID>.<Graph_instance_name>. Sometimes it is shown as _main and then cross-probe is required to find the real kernel function.

Start (ps)

The start time that the stall happens

Duration (ps)

The duration of the stall.

PC

Program counter when the stall happens.

Bank Conflict

The memory bank where the stall happens on.

Buffer 1, Buffer 2, Buffer 3

The buffers that cause the memory stall. It can be one buffer or multiple buffers.
When you click each line of the stalls in the Stalls view, it goes to the start of the memory stall in the Trace view. Zoom in and out of the Trace view to observe how frequently the memory stalls occur and the position of the stall in kernel running.
Note: If large number of memory stalls occur repeatedly in the running kernel, it indicates that the stalls can happen inside loop. It is best to investigate and resolve. If memory stalls only happen once at the start of the kernel running, or a very small number of stalls happen in kernel running, it can usually be neglected. From the name of the buffers that cause the stall, it can be identified whether it is window buffer or system buffer or something else. If it is a window buffer or RTP buffer that can be controlled in the graph, one way is to place it manually using constraints if better placement can be identified. If it is system memory (named system<NUM>+<NUM>), it is required to identify the variables that are involved in the stall.
Click the row of the specific stall and switch to the Events view.
Figure 2. Events View of Memory Stall
The Events view shows the events that happen in the device. The cycle where the memory stall happens is highlighted. You can see the tile on which the DM_BANK_CONFLICT event has occurred and the data that is being read or written.
Try to explore some cycles before or after the stall cycle to find more hints.

In some cases, the tool schedules to read or write variables at the same bank in a cycle. One way to resolve it is documented in the Load and Store with Virtual Resource Annotations section in AI Engine Kernel and Graph Programming Guide (UG1079). For example, redefine points to the variables and annotate them with __aie_dm_resource_a. Following is an example code：
```
const v8cint16 __aie_dm_resource_a* __restrict coeff = (v8cint16 __aie_dm_resource_a*) eq_coef0; const v8cint16 coe = *coeff;
v16cint16 __aie_dm_resource_a* __restrict p_buff = (v16cint16 __aie_dm_resource_a*) &delay_line; v16cint16 buff=*p_buff;
```

The following table lists some possible scenarios that cause memory stalls and possible solutions.

Table 1. Memory Stall Scenarios and Solutions
Source	Target	Stall Type	Possible Solution	Note
One kernel	Buffers on one memory bank	Memory stall	Dispatch memories to different banks (memories include system memory, RTP, window buffer, DMA, and FIFO). See Memory Stalls. Guide compiler scheduling with virtual memory annotations. See Load and Store with Virtual Resource Annotations section in AI Engine Kernel and Graph Programming Guide (UG1079)	One kernel accesses memories on the same bank. Or one kernel has multiple accesses on one memory on the same bank. (a cycle can have two loads and one store)
Multiple kernels on adjacent AI Engine tiles	Multiple buffers on one bank	Memory stall	Dispatch memories to different banks (memories include system memory, RTP, window buffer, DMA, and FIFO). BufferOptLevel. See Mapper and Router Options. If memory banks are exhausted, do profile and AI Engine stall analysis to find better solution with less kernel execution time or less stall percentage.	Multiple kernels accessing multiple memories on the same bank.