The SVM function is the SVM core operation, which performs dot
product between the input arrays. The function returns the resultant dot
product value with its fixed point type.
API Syntax
template<int SRC1_T, int SRC2_T, int DST_T, int ROWS1, int COLS1, int ROWS2, int COLS2, int NPC=1, int N, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_2 = _XFCVDEPTH_DEFAULT>
void SVM(xf::cv::Mat<SRC1_T, ROWS1, COLS1, NPC, XFCVDEPTH_IN_1> &in_1, xf::cv::Mat<SRC2_T, ROWS2, COLS2, NPC, XFCVDEPTH_IN_2> &in_2, uint16_t idx1, uint16_t idx2, uchar_t frac1, uchar_t frac2, uint16_t n, uchar_t *out_frac, ap_int<XF_PIXELDEPTH(DST_T)> *result)
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameters | Description |
|---|---|
| SRC1_T | Input pixel type. 16-bit, signed, 1 channel (XF_16SC1) is supported. |
| SRC2_T | Input pixel type. 16-bit, signed, 1 channel (XF_16SC1) is supported. |
| DST_T | Output data Type. 32-bit, signed, 1 channel (XF_32SC1) is supported. |
| ROWS1 | Number of rows in the first image being processed. |
| COLS1 | Number of columns in the first image being processed. |
| ROWS2 | Number of rows in the second image being processed. |
| COLS2 | Number of columns in the second image being processed. |
| NPC | Number of pixels to be processed per cycle; possible options are XF_NPPC1. |
| N | Max number of kernel operations |
| XFCVDEPTH_IN_1 | Depth of the input image. |
| XFCVDEPTH_IN_2 | Depth of the input image. |
| in_1 | First Input Array. |
| in_2 | Second Input Array. |
| idx1 | Starting index of the first array. |
| idx2 | Starting index of the second array. |
| frac1 | Number of fractional bits in the first array data. |
| frac2 | Number of fractional bits in the second array data. |
| n | Number of kernel operations. |
| out_frac | Number of fractional bits in the resultant value. |
| result | Resultant value |
Resource Utilization
The following table summarizes the resource utilization of the SVM function, generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA.
| Operating Frequency (MHz) | Utilization Estimate (ms) | ||||
|---|---|---|---|---|---|
| BRAM_18K | DSP_48Es | FF | LUT | CLB | |
| 300 | 0 | 1 | 27 | 34 | 12 |
Performance Estimate
The following table summarizes the performance in different configurations, as generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA.
| Operating Frequency (MHz) | Latency Estimate | |
|---|---|---|
| Min (cycles) | Max (cycles) | |
| 300 | 204 | 204 |