Sum - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

The sum function calculates the sum of all pixels in input image.

API Syntax

template< int SRC_T , int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT>
void sum(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & src1,double sum[XF_CHANNELS(SRC_T,NPC)])

Parameter Descriptions

The following table describes the template and the function parameters.

Table 731 Table . Sum Parameter Description
Parameter Description
SRC_T Input pixel type. 8-bit, unsigned 1 and 3 channels are supported (XF_8UC1,XF_8UC3).
ROWS Maximum height of input and output image.
COLS Maximum width of input and output image (must be multiple of 8).
NPC Number of pixels to be processed per cycle XF_NPPC1 XF_NPPC8 are supported
XFCVDEPTH_IN Depth of the input image.
_src1 Input image.
sum Array to store sum of all pixels in the image.

Resource Utilization

The following table summarizes the resource utilization of the Sum function in Resource optimized (8 pixel) mode and normal mode as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.

Table 732 Table . Sum Function Resource Utilization Summary
Name Resource Utilization
1 pixel per clock operation 8 pixel per clock operation
300 MHz 150 MHz
BRAM_18K 0 0
DSP48E 0 0
FF 341 408
LUT 304 338
CLB 71 87

Performance Estimate

The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.

Table 733 Table . Sum Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz)  
8 pixel operation (150 MHz)