The Demosaicing function converts a single plane Bayer pattern output, from the digital camera sensors to a color image. This function implements an improved bi-linear interpolation technique proposed by Malvar, He, and Cutler.
The above figure shows the Bayer mosaic for color image capture in single-CCD digital cameras.
API Syntax
template<int BFORMAT, int SRC_T, int DST_T, int ROWS, int COLS, int NPC, bool USE_URAM=false, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void demosaicing(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> &src_mat, xf::cv::Mat<DST_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> &dst_mat)
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameter | Description |
|---|---|
| BFORMAT | Input Bayer pattern. XF_BAYER_BG, XF_BAYER_GB, XF_BAYER_GR, and XF_BAYER_RG are the supported values. |
| SRC_T | Input pixel type. 8-bit, unsigned,1 channel (XF_8UC1) and 16-bit, unsigned, 1 channel (XF_16UC1) are supported. |
| DST_T | Output pixel type. 8-bit, unsigned, 4 channel (XF_8UC4) and 16-bit, unsigned, 4 channel (XF_16UC4) are supported. |
| ROWS | Number of rows in the image being processed. |
| COLS | Number of columns in the image being processed. Must be multiple of 8, in case of 8 pixel mode. |
| NPC | Number of pixels to be processed per cycle; single pixel parallelism (XF_NPPC1), two-pixel parallelism (XF_NPPC2) and four-pixel parallelism (XF_NPPC4) are supported. XF_NPPC4 is not supported with XF_16UC1 pixel type. |
| USE_URAM | Enable to map storage structures to UltraRAM. |
| XFCVDEPTH_IN_1 | Depth of input image |
| XFCVDEPTH_OUT_1 | Depth of output image |
| _src_mat | Input image |
| _dst_mat | Output image |
. rubric:: Resource Utilization
The following table below shows the resource utilization of the Demosaicing function, generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.
| Operating Mode | Operating Frequency (MHz) | Utilization Estimate | ||||
|---|---|---|---|---|---|---|
| BRAM_18K | DSP_48Es | FF | LUT | CLB | ||
| 1 Pixel | 300 | 8 | 0 | 1906 | 1915 | 412 |
| 2 Pixel | 300 | 8 | 0 | 2876 | 3209 | 627 |
| 4 Pixel | 300 | 8 | 0 | 2950 | 3222 | 660 |
The following table shows the resource utilization of the Demosaicing function, generated using Vivado HLS 2019.1 version tool for the xczu7ev-ffvc1156-2-e FPGA.
| Operating Mode | Operating Frequency (MHz) | Utilization Estimate | |||||
|---|---|---|---|---|---|---|---|
| BRAM_18K | URAM | DSP_48Es | FF | LUT | CLB | ||
| 1 Pixel | 300 | 0 | 1 | 0 | 1366 | 1399 | 412 |
Performance Estimate
The following table shows the performance in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 to process a 4K (3840x2160) image.
| Operating Mode | Latency Estimate |
|---|---|
| Max Latency (ms) | |
| 1 pixel operation (300 MHz) | 27.82 |
| 2 pixel operation (300 MHz) | 13.9 |
4 pixel operation (300 MHz, 8-bit image only) |
6.95 |