Accumulate Weighted - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

The accumulateWeighted function computes the weighted sum of the input image (src1) and the accumulator image (src2) and generates the result in dst.


image7

The accumulated result is a separate argument in the function, instead of having src2 as the accumulated result. In this implementation, having a bi-directional accumulator is not possible, as the function uses streams.

API Syntax

template<int SRC_T, int DST_T, int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_2 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void accumulateWeighted (
xf::cv::Mat< SRC_T,  ROWS,  COLS,  NPC,  XFCVDEPTH_IN_1>& src1,
xf::cv::Mat< SRC_T,  ROWS,  COLS,  NPC,  XFCVDEPTH_IN_2>& src2,
xf::cv::Mat< DST_T,  ROWS,  COLS,  NPC,  XFCVDEPTH_OUT_1>& dst,
float alpha )

Parameter Descriptions

The following table describes the template and the function parameters.

Table 278 Table accumulateWeighted Parameter Description
Parameter Description
SRC_T Input pixel type. Only 8-bit, unsigned, 1 and 3 channels are supported (XF_8UC1 and XF_8UC3)
DST_T Output pixel type. Only 16-bit, unsigned, 1 and 3 channels are supported (XF_16UC1 and XF_16UC3)
ROWS Maximum height of input and output image.
COLS Maximum width of input and output image. Recommend multiples of 8, for an 8-pixel operation.
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8 for 1,2,4 pixel and 8 pixel operations respectively.
XFCVDEPTH_IN_1 Depth of the input image
XFCVDEPTH_IN_2 Depth of the input image
XFCVDEPTH_OUT_1 Depth of the output image
src1 Input image
src2 Input image
dst Output image
alpha Weight applied to input image

Resource Utilization

The following table summarizes the resource utilization in different configurations, generated using Vivado HLS 2019.1 tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a grayscale HD (1080x1920) image.

Table 279 Table accumulateWeighted Function Resource Utilization Summary
Operating Mode Operating Frequency (MHz) Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 Pixel 300 0 5 295 255 52
8 Pixel 150 0 19 556 476 88

The following table summarizes the resource utilization in different configurations, generated using Vivado HLS 2019.1 tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a 4K 3 Channel image.

Table 280 Table accumulateWeighted Function Resource Utilization Summary
Operating Mode Operating Frequency (MHz) Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 Pixel 300 0 9 457 387 95

Performance Estimate

The following table summarizes the performance in different configurations, as generated using Vivado HLS 2019.1 tool for the Xczu9eg-ffvb1156-1-i-es1, to process a grayscale HD (1080x1920) image.

Table 281 Table accumulateWeighted Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7

Deviation from OpenCV

The resultant image in OpenCV is stored in the second input image. The src2 image acts as input as well as output, as shown below:

image8

Whereas, in Vitis Vision implementation, the accumulated weighted image is stored separately.

image9