convertScaleAbs - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

The convertScaleAbs function converts an input image src with optional linear transformation, save the result as image dst.

dst(x,y)= src1(x,y)*scale+shift

API Syntax

template< int SRC_T,int DST_T, int ROWS, int COLS, int NPC = 1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void convertScaleAbs(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> & src1, xf::cv::Mat<DST_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> & dst,float scale, float shift)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 470 Table . convertScaleAbs Parameter Description
Parameter Description
SRC_T Input pixel type. Only 8-bit, unsigned, 1 channel is supported (XF_8UC1).
DST_T Output pixel type. Only 8-bit, unsigned, 1 channel is supported (XF_8UC1).
ROWS Maximum height of input and output image.
COLS Maximum width of input and output image. In case of N-pixel parallelism, width should be multiple of N.
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8 for 1,2,4 pixel and 8 pixel operations respectively.
XFCVDEPTH_IN_1 Depth of input image
XFCVDEPTH_OUT_1 Depth of output image
src1 Input image
scale Scale factor
shift Delta/shift added to scaled value.
dst Output image

Resource Utilization

The following table summarizes the resource utilization of the convertScaleAbs function in Resource optimized (8 pixel) mode and normal mode as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.

Table 471 Table . convertScaleAbs Function Resource Utilization Summary
Name Resource Utilization
1 pixel per clock operation 8 pixel per clock operation
300 MHz 150 MHz
BRAM_18K 0 0
DSP48E 10 38
FF 949 1971
LUT 1052 1522
CLB 218 382

Performance Estimate

The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image…

Table 472 Table . convertScaleAbs Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7