Compare - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

The Compare function performs the per element comparison of pixels in two corresponding images src1, src2 and stores the result in dst.

dst(x,y)=src1(x,y) CMP_OP src2(x,y)

CMP_OP – a flag specifies correspondence between the pixels.

  • XF_CMP_EQ : src1 is equal to src2
  • XF_CMP_GT : src1 is greater than src2
  • XF_CMP_GE : src1 is greater than or equal to src2
  • XF_CMP_LT : src1 is less than src2
  • XF_CMP_LE : src1 is less than or equal to src2
  • XF_CMP_NE : src1 is unequal to src2

If the comparison result is true, then the corresponding element of dst is set to 255; else it is set to 0.

API Syntax

void compare(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> & _src1, xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_2> & _src2, xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> & _dst)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 464 Table Compare Parameter Description
Parameter Description
CMP_OP The flag that specify the relation between the elements needs to be checked
SRC_T Input and output pixel type. Supports 1 channel and 3 channels (XF_8UC1,XF_16SC1,XF_16SC3 and XF_8UC3)
ROWS Maximum height of input and output image.
COLS Maximum width of input and output image (must be a multiple of 8, for 8 pixel mode)
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8 for 1,2,4 pixel and 8 pixel operations respectively.
XFCVDEPTH_IN_1 Depth of input image
XFCVDEPTH_IN_2 Depth of input image
XFCVDEPTH_OUT_1 Depth of output image
_src1 First input image
_src2 Second input image
_dst Output image

Resource Utilization

The following table summarizes the resource utilization of the Compare XF_CMP_NE configuration in Resource optimized (8 pixels) mode and normal mode as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.

Table 465 Table Compare Function Resource Utilization Summary
Name Resource Utilization
1 pixel per clock operation 8 pixel per clock operation
300 MHz 150 MHz
BRAM_18K 0 0
DSP48E 0 0
FF 87 60
LUT 38 84
CLB 16 20

Performance Estimate

The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.

Table 466 Table Compare Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7