Executable Usage - 2023.2 English

Vitis Libraries

Release Date
2023.2 English
  • Work Directory(Step 1)

The steps for library download and environment setup can be found in README of L3 folder. For getting the design,

cd L3/examples/isppipeline
  • Build kernel(Step 2)

Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.

export OPENCV_INCLUDE=< path-to-opencv-include-folder >
export OPENCV_LIB=< path-to-opencv-lib-folder >
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:< path-to-opencv-lib-folder >
export PLATFORM=< path-to-platform-directory >/< platform >.xpfm
make host xclbin TARGET=hw
  • Run kernel(Step 3)

To get the benchmark results, please run the following command.

make run TARGET=hw
  • Example output(Step 4)
-----------ISP Pipeline Design--------------------------------------------------------------------------------
Found Platform
Platform Name: Xilinx
XCLBIN File Name: krnl_ISPPipeline
INFO: Importing vision/L3/examples/isppipeline/build_dir.hw.xilinx_u200_xdma_201830_2/krnl_ISPPipeline.xclbin
Loading: 'vision/L3/examples/isppipeline/build_dir.hw.xilinx_u200_xdma_201830_2/krnl_ISPPipeline.xclbin'
The maximum depth reached by any of the 8 hls::stream() instances in the design is 196608