Internals of streamCombine - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

The streamCombine function is designed for packing multiple elements of same width into a vector.

This module offers two static configurations: using the data from LSB or MSB. With LSB option, the element at LSB is obtained from input stream with 0 index, while with MSB option, the element at MSB is set using input with 0 index.

As some storage structures in FPGA are bounded to fixed width or width of power of two, paddings may be necessary sometimes in the combined vector. These padding bits are added with zeros, as illustrated below:

combination n streams to one from LSB Structure combination n streams to one from MSB Structure

Internally, this module is implemented with a simple loop which initiation interval (II) is equal to 1. This means that in each cycle, a vector is yielded using a set of elements.


This module expects the width of output stream to be no less than total of input streams. To perform collection from multiple streams, consider the streamNToOne module.