Vector Output - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

The design of the primitive includes 3 modules:

  1. fetch: attempt to read data from the n input streams.
  2. vectorize: Inner buffers as wide as the least common multiple of N * Win and Wout are used to combine the inputs into vectors.
  3. emit: read vectorized data and emit to output stream.
structure of vectorized round-robin collection


Current implementation has the following limitations:

  • It uses a wide ap_uint as internal buffer. The buffer is as wide as the least common multiple (LCM) of input width and total output width. The width is limited by AP_INT_MAX_W, which defaults to 1024.
  • This library will try to override AP_INT_MAX_W to 4096, but user should ensure that ap_int.h has not be included before the library headers.
  • Too large AP_INT_MAX_W will significantly slow down HLS synthesis.