Column Vector Buffering and Distribution Implementation - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

This page provides the column vector buffering and distribution implementation details. The following figure shows the column vector buffering and distribution logic.

cscRow Diagram
  • The input parameter streams contain the information of the size of each column vector block, the minimum and maximum column vector entry indices.
  • The dispColVec module reads the parameters and multiple column vector enties, buffers the column entires in its own on-chip memory and forward the rest parameters and vector entires to the next disColVec module. If the module is the last one in the chain, the forwarding logic is omitted.
  • After the buffereing operation, each dispColVec module reads out the data from the on-chip memory and sends them to the output stream to be processed by its own computation path.
  • Apart from buffering and reading data operations, the dispColVec module also aligns the data and pads the data according to SPARSE_parEntries and the minimumn and maximum row indices.