Implementation on FPGA - 2023.2 English

Vitis Libraries

Release Date
2023.2 English

We support XTS-AES128 and XTS-AES256 modes in this implementation.


The bit-width of the interfaces we provide is shown as follows:

  plaintext ciphertext cipherkey IV textlength
CBC-AES128 128 128 128 128 64
CBC-AES256 128 128 256 128 64

The algorithm flow chart is shown as follow:

algorithm flow chart of XTS

As we can see from the chart, the dependency of XTS encryption flow only exists between the first block and the second to last block. It is same as shown in XTS decryption flow. Therefore, the initiation interval (II) of XTS encryption and decryption mode can achieve 1. Notice that one one-word AES encryption module is instanced in XTS decryption.