Implementation on FPGA - 2023.2 English

Vitis Libraries
Release Date
2023-12-20
Version
2023.2 English

We support CTR-AES128, CTR-AES192, and CTR-AES256 modes in this implementation.

Attention

The bit-width of the interfaces we provide is shown as follows:

  plaintext ciphertext cipherkey IV
CTR-AES128 128 128 128 128
CTR-AES192 128 128 192 128
CTR-AES256 128 128 256 128

The algorithm flow chart is shown as follow:

algorithm flow chart of CTR

As we can see from the chart, both encryption and decryption part of CTR mode has no dependencies, so the input block of each iteration can be directly calculated by the counter. Thus, both encryption and decryption part of CTR mode can achieve an initiation interval (II) = 1.